The present invention relates generally to improved means and methods for providing data processing in a microprogrammed electronic digital processor. More particularly, the present invention is directed to an improved interpretive-type processor employing a hierarchy of processor levels.
As is well known, an interpretive processor provides for supporting multiple high level languages through the use of a number of interpreters, each of which is designed to support one or more high level languages. The Burroughs B 1700 and B 1800 computer systems are examples of commercially available computers of this type. As is typical of an interpretive processor, each input high level language (source program) executes on a virtual (soft) processor (referred to as an S-processor in the Burroughs B 1700) which has its own special set of instructions (called S-instructions or S-ops in the B 1700) that are specially tailored to the needs of the respective input high level language or languages to be interpreted thereby. Typically, there may be a number of different S-processors. For example, in a typical system there may be separate S-processors for COBOL and FORTRAN.
Descriptions of processors in general and the Burroughs B 1700 in particular may be found, for example, in the article "Design of the Burroughs B 1700," W. T. Wilner, AFIPS Conference Proc., 1972, Vol. 41, Part I, pp. 489-497; in the book "Foundations of Microprogramming," Agrausala, et al., Academic Press, Inc., 1976, pp. 120-139; and also in the article "Microprogramming-Another Look at Internal Computer Control," Michael J. Flynn, IEEE Proc., Vol. 63, No. 11, November, 1975, pp. 1554-1567. Also, the commonly assigned U.S. Pat. Nos. 3,665,421; 3,680,058; 3,735,363; 3,739,352; 3,781,812; and 3,792,441 are directed to various features of an interpretive processor. The subject matter of these articles and patents are to be considered as incorporated herein. In addition, the commonly assigned copending application Ser. No. 830,157, filed Sept. 2, 1977, now U.S. Pat. No. 4,181,935, issued Jan. 1, 1980, W. E. Feeser and M. L. C. Gerhold, inventors, discloses an interpretive processor employing a cache-type of microinstruction control memory.